A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, is capable of storing two bits of data in a double-bit arrangement. That is, one bit can be stored using a first charge storing region on a first “side” of the memory device and a second bit can be stored using a second charge storing region on a second “side” of the memory device.
As shown in FIG. 2, in a conventional charge trapping dielectric flash memory device 10, the charge storing regions 36, 38 are part of a non-conductive charge trapping layer 28 that is disposed between a relatively thick (e.g., about 100 angstroms (Å)) bottom (or tunnel) dielectric layer 26 and a relatively thick (e.g., 100 angstroms (Å)) top dielectric layer 30. This dielectric stack can be formed over a P-type conductivity silicon substrate 12 having a series of bitlines BL1, BL2 disposed therein. A series of conductive wordlines WL made from polycrystalline silicon is formed over the dielectric stack for serving as a gate electrode 32 for each memory device. The core memory devices 10 can be addressed by applying appropriate voltages to the wordline WL and/or bitlines BL1, BL2. During programming and reading of the core memory devices 10, the bitlines BL1, BL2 can function as a source 14 (i.e., a source of electrons or holes) and a drain 16 with an active channel region defined therebetween.
Programming of such a memory device 10 can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate electrode 32, the source 14, and the drain 16 of the memory device 10 for a specified duration until the charge trapping layer 28 accumulates charge.
A conventional charge trapping dielectric flash memory device 10 can be erased using the conventional technique of “hot hole injection” (sometimes referred to as band-to-band (BTB) hot hole injection). In a hot hole injection erase, a negative gate 32 voltage (e.g., about −4 Volts to about −8 Volts) is applied along with a drain 16 voltage on the order of about 4.5 Volts to about 6.0 Volts, while the source is floated or grounded to erase one of the memory cells (typically the normal bit 36). Conversely, the complementary bit cell 38 is erased by floating the drain and applying the appropriate voltages to the source 14 and the gate 32.
As shown in FIG. 2, with such erase conditions, a BTB tunnel current is created under the gate. Holes 22 are generated under these conditions and accelerate from the N-type drain 16 region into the P-type body 18. The generated holes 22 are accelerated in the electrical field created near the P-N drain/body junction. Some of the accelerated holes 22 surmount the bottom dielectric to silicon interface between the substrate 12 and the bottom dielectric layer 26 and are injected into the charge trapping layer 28 to displace electrons (e.g., by recombination) and erase the cell. However, as these hot holes bombard the interface between the substrate 12 and the bottom tunnel dielectric 26, the interface as well as the bottom tunnel dielectric are damaged, causing undesirable interface states, degraded reliability over program/erase cycling, and diminished data retention capability.
Accordingly, there is an ever increasing demand for a charge trapping dielectric flash memory device, which can be erased effectively, while more effectively maintaining data retention capability.